1. Field of the Invention
The present invention relates to a semiconductor device and a production process therefor. More particularly, the invention relates to a semiconductor device such as a dynamic threshold voltage transistor in which a gate electrode is connected to a well region and a production process therefor.
2. Description of Related Art
For reducing power consumed by a CMOS circuit using a MOSFET, decreasing supply voltage is one of the most effective means. However, if the supply voltage is simply decreased, a driving current for the MOSFET declines and the operating speed of the circuit slows. It is known that this phenomenon becomes notable where the supply voltage becomes lower than the triple of the threshold voltage of a transistor.
In order to prevent this phenomenon, the threshold voltage may be lowered. However, a decline in the threshold voltage may give rise to a problem that leakage current when the MOSFET is off (also referred to as off-leak hereinafter) increases. For this reason, the lower limit of the threshold voltage is restricted within such a range that this problem does not occur. Such restriction to the lower limit of the threshold voltage also sets limits to reduction of power consumption since it corresponds to the lower limit of the supply voltage.
In order to provide relief from this problem, conventionally proposed is a dynamic threshold voltage MOSFET (DTMOS) using an SOI substrate which allows a high driving current to be produced from a low supply voltage by reduction of an effective threshold when the MOSFET is on (A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation by F. Assaderaghi et al., IEDM94 Ext. Abst. P.809(1994)). Also proposed are dynamic threshold voltage transistors without using the expensive SOI substrate but using bulk substrates (Japanese Unexamined Patent Publication No. HEI 10(1998)-22462 and Novel Bulk Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS by H. Kotaki et al., IEDM Tech. Dig., p.459, 1996). Both the MOSFETS can reduce the effective threshold voltage when they are on, because gate electrodes and substrates (or well regions) are electrically short-circuited.
FIGS. 27(a) and 27(b) show N-type dynamic threshold voltage transistors using the former SOI substrate. FIG. 27(a) shows a transistor of a complete depletion type and FIG. 27(b) shows a transistor of a partial depletion type. In the figures, reference numeral 111 denotes a substrate, 112 denotes a buried oxide film layer, 113 denotes a body, 114 denotes a source region, 115 denotes a drain region, 116 denotes a gate insulating film, and 117 denotes a gate electrode. The gate electrode 117 is electrically connected to the p-type body 113 via a contact hole, though not shown. Here, the complete depletion means that the body is completely depleted beneath the gate electrode and the partial depletion means that the body is partially undepleted beneath the gate electrode. It is noted that P-type transistors can be formed by reversing polarity (a type of conductivity) shown in the figures.
FIG. 28 shows an N-type dynamic threshold voltage transistor using the latter bulk substrate. It is noted that a P-type transistor can be formed by reversing the polarity (a type of conductivity) shown in the figure. In the figure, reference numeral 211 denotes a substrate, 212 denotes an N-type well region (a deep well region), 213 denotes a P-type well region (a shallow well region), 214 denotes a buried high-concentration region, 215 denotes a trench isolation region, 216 denotes a source region, 217 denotes a drain region, 218 is a gate insulating film and 219 denotes a gate electrode. The gate electrode 219 is electrically connected to the shallow well region 213 via a contact hole though this connection is not shown. A transistor formed in a single shallow well region is simply referred to as a device hereinafter.
Now explanation is given to the principle of operation of the dynamic threshold voltage transistor using the bulk substrate. It is noted that the transistor using the SOI substrate also operates on substantially the same principle. In the above-mentioned transistor, when the potential of the gate electrode is at a low level (when the transistor is off), the potential of the shallow well region is also at a low level. Accordingly, the effective threshold voltage does not differ from that of a common MOSFET, and the value of leakage current is the same as that of the common MOSFET.
When the potential of the gate electrode is at a high level (when the transistor is on), the potential of the shallow well region is also at a high level. The effective threshold voltage decreases due to a substrate bias effect and the driving current increases as compared with the common MOSFET. Therefore, a large driving current can be obtained at a low supply voltage while a low leakage current is maintained.
Next, explanation is given to device isolation with the dynamic threshold voltage transistor using the bulk substrate. The potential in the shallow well region varies depending on the potential of the gate electrode. For this reason, a trench isolation region is formed between devices for isolating them to prevent interference therebetween. The depth of the trench isolation region is set such that the shallow well regions of adjacent devices are electrically separated. That is, the depth of the trench isolation region is so set that a depletion layer extending from a junction of the shallow well region and the deep well region does not contact to a depletion layer extending from a junction of the shallow well region with the deep well region of the adjacent device.
For making the most of the substrate bias effect and realizing a high-speed operation, a change in the potential of the gate electrode must be transmitted to the shallow well region quickly. For this purpose, the buried high-concentration region is constructed to be sandwiched by regions having low impurity concentrations, in FIG. 28. This construction enables electrical resistance in the shallow well region to decrease and a change in the potential of the gate electrode to be transmitted to the shallow well region immediately. At the same time, since the impurity concentration in a channel region can be reduced, a low threshold can be realized and a junction capacitance between the source region and the shallow well region and a junction capacitance between the drain region and the shallow well region can be kept small.
As described above, in operation of the dynamic threshold voltage transistor, a change in the potential of the gate electrode is required to be transmitted to the shallow well region quickly. Time necessary for this transmission is explained with use of FIGS. 29(a) and 29(b). FIG. 29(a) is a schematic diagram of a dynamic threshold voltage transistor using a bulk substrate and FIG. 29(b) is an equivalent circuit diagram thereof. In the figures, reference numeral 311 denotes a deep well region, 312 denotes a shallow well region, 313 denotes a source region, 314 denotes a drain region, 315 denotes a gate insulating film, 316 denotes a gate electrode, 317 denotes a gate input terminal, 318 denotes a depletion layer region extending from a junction of the source region and the shallow well region, 319 denotes a depletion layer region extending from a junction of the drain region with the shallow well region, 320 denotes a gate depletion layer region, 321 denotes a depletion layer region extending from a junction of the shallow well region and the deep well region, 322 denotes a source input terminal, 323 denotes a drain input terminal, 324 denotes a terminal of the deep well region, 325 denotes a charge inversion layer, 326 denotes the capacitance of the depletion layer extending from the junction of the source region and the shallow well region, 327 denotes the capacitance of the depletion layer extending from the junction of the drain region and the shallow well region, 328 denotes the capacitance of the gate depletion layer, 329 denotes the capacitance of the gate, 330 denotes the capacitance of the depletion layer extending from the junction of the shallow well region and the deep well region, 331 denotes the resistance of the shallow well region, and 332 denotes the resistance of the gate electrode. It is noted that a device isolation region is not shown in these figures.
Time .tau. which is necessary for a potential given to the gate input terminal 317 to be transmitted to the shallow well region is represented by the following formulae: EQU .tau.=CR EQU C=Cs+Cd+Cdep+Csw/dw
, wherein C is the sum of the junction capacitance Cs between the source region and the shallow well region (body), the junction capacitance Cd between the drain region and the shallow well region (body), the capacitance Cdep of the gate depletion layer, and the junction capacitance Csw/dw between the shallow well region and the deep well region (only in the case of a dynamic threshold voltage transistor using a bulk substrate), and R is the resistance of the shallow well region (body). Besides, the time necessary for charging the capacitance Cg of the gate is represented by the product of the capacitance Cg, and resistance Rg of the gate and is usually shorter than .tau..
Time .tau. must be sufficiently shorter than the time necessary for having charged the capacitance for the next stage when the transistor becomes on. In other words, it must be sufficiently shorter than the sum of time constants related to the capacitance of the gate, the capacitance of wiring and the like. If this condition is not satisfied, the operation speed of the circuit declines considerably because a sufficient substrate bias effect is not obtained before the switching of operation is finished.
The above-described dynamic threshold voltage transistor using an SOI substrate is said to have a problem that its body has a high resistance. In the case of the complete depletion type, the body is so thin, say 30 nm, that it is impossible to adjust the threshold by raising the impurity concentration in the body for the purpose of reducing the resistance of the body. On the other hand, in the case of the partial depletion type, the body has a relatively large thickness, say 100 to 150 nm. However, even if the impurity concentration in the body is raised to 1.times.10.sup.18 cm.sup.-3, .tau. is about 1.times.10.sup.-10 sec supposing C is 1.times.10.sup.-15 F, in the case of a device having a gate length of 0.18 .mu.m and a gate width of 1.8 .mu.m, for example. This .tau. is large as compared with other delay factors and therefore the substrate bias effect can hardly be obtained. In addition, when the impurity concentration in the body is high, the depletion layers extending from the junctions with the source region and with the drain region do not contact the buried oxide film layer, and therefore the junction capacitances increase greatly. If the junctions of the source and drain regions with the body are located deeper with a view to preventing this, a short-channel effect increases considerably.
For these reasons, it is difficult to obtain a sufficiently short .tau. with the dynamic threshold voltage transistor using the SOI substrate.
On the other hand, in the case of the dynamic threshold voltage transistor using a bulk substrate (hereafter referred to as a B-DTMOS), no limit is placed on the depth of the shallow well region. Accordingly, if a high-concentration impurity layer is formed at a sufficiently deep location, the resistance of the shallow well region can be reduced without giving any effect on the impurity concentration in the channel region. Thereby .tau. can be sufficiently decreased.
Clearly, in order to reduce the resistance of the shallow well region, the dose of implanted impurity may be increased. However, it has been found that the leakage current when the transistor is off increases rapidly as the implantation dose is increased.
FIG. 5 represents an Id (drain current)-Vg (gate voltage) characteristic of an N-type B-DTMOS produced under the following implantation conditions of shallow well region: An impurity ion species of .sup.11 B.sup.+ ; an implantation energy of 250 KeV; and an implantation dose of 1.times.10.sup.14 cm.sup.-2. In this case, the off-leak is 9.times.10.sup.-10 A/.mu.m of gate width. Where the supply voltage is 0.5V, the ratio of the driving current to the off-leak current is about 10.sup.4. This current ratio is far from a standard requisite for a power-saving device, 10.sup.5.
Thus, in a method wherein the implantation dose of the impurity is increased for reducing the resistance of the shallow well region and improving the speed of transmission of a change in the potential of the gate electrode, there arises a problem that the off-leak increases. In addition to that, because a depletion layer extending from the shallow well region and the deep well region becomes deeper, there arises a problem that the trench device isolation region must be deepened.